ST STM32F100 Series Reference Manual page 341

RM0041
Offset Register
TIMx_CNT
0x24
Reset value
TIMx_PSC
0x28
Reset value
TIMx_ARR
0x2C
Reset value
0x30
TIMx_CCR1
0x34
Reset value
TIMx_CCR2
0x38
Reset value
TIMx_CCR3
0x3C
Reset value
TIMx_CCR4
0x40
Reset value
0x44
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value
Refer to for the register boundary addresses.
Table 73. TIMx register map and reset values (continued)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
General-purpose timers (TIM2 to TIM5)
0 0
0 0
1 1
Reserved
0 0
0 0
0 0
0 0
Reserved
0 0
RM0041 Rev 6
CNT[15:0]
0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0
ARR[15:0]
1 1 1 1 1 1 1 1
CCR1[15:0]
0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0 0
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