Tim13/14 Capture/Compare Register 1 (Timx_Ccr1) - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus
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General-purpose timers (TIM12/13/14)
14.5.10

TIM13/14 capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34
Reset value: 0x0000
15
14
13
rw/ro
rw/ro
rw/ro
rw/ro
Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1
register is read-only and cannot be programmed.
386/709
12
11
10
9
rw/ro
rw/ro
rw/ro
8
7
6
CCR1[15:0]
rw/ro
rw/ro
rw/ro
rw/ro
RM0041 Rev 6
5
4
3
2
rw/ro
rw/ro
rw/ro
RM0041
1
0
rw/ro
rw/ro

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