Tim12 Slave Mode Control Register (Timx_Smcr) - ST STM32F100 Series Reference Manual

General-purpose timers (TIM12/13/14)
14.4.3

TIM12 slave mode control register (TIMx_SMCR)

Address offset: 0x08
Reset value: 0x0000
15 14 13
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 MSM: Master/Slave mode
Bits 6:4 TS: Trigger selection
Note: These bits must be changed only when they are not used (e.g. when SMS='000') to
366/709
12 11 10 9
Reserved
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful in
order to synchronize several timers on a single external event.
This bit field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: Reserved.
See Table 74: TIMx Internal trigger connection on page
of ITRx for each timer.
avoid wrong edge detections at the transition.
8 7 6
MSM TS[2:0]
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RM0041 Rev 6
5 4 3 2
Res.
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367for more details on the meaning
RM0041
1 0
SMS[2:0]
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