Figure 191. Counter Timing Diagram, Internal Clock Divided By 4; Figure 192. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F100 Series Reference Manual

RM0041 Basic timers (TIM6 and TIM7)

Figure 191. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
0035 0036 0000 0001
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MSv37301V1

Figure 192. Counter timing diagram, internal clock divided by N

CK_INT
Timerclock = CK_CNT
Counter register 1F 20 00
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MSv37302V1
Figure 193. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
31 32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
FF 36
Write a new value in TIMx_ARR
MSv37303V1
RM0041 Rev 6 461/709
468