Tim15 And External Trigger Synchronization (Only For Tim15); Figure 183. Control Circuit In Reset Mode - ST STM32F100 Series Reference Manual

RM0041
15.4.14

TIM15 and external trigger synchronization (only for TIM15)

The TIM15 timer can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
•
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don't need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so no need to configure it. The CC1S bits select the
input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 in
TIMx_CCER register to validate the polarity (and detect rising edges only).
• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
•
Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 183. Control circuit in reset mode

TI1
UG
Counter clock = ck_cnt = ck_psc
Counter register
TIF
General-purpose timers (TIM15/16/17)
30 31 32 33 34 35 36
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00 01 02 03 00 01 02 03
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