Table 30. Tim5 Alternate Function Remapping; Table 31. Tim12 Remapping; Table 32. Tim13 Remapping; Table 33. Tim14 Remapping - ST STM32F100 Series Reference Manual

RM0041
Alternate function
TIM5_CH4
1. Remap available only for high-density value line devices.
Alternate function
TIM12_CH1
TIM12_CH2
1. Refer to the AF remap and debug I/O configuration register
configuration register
Alternate function
TIM13_CH1
1. Refer to the AF remap and debug I/O configuration register
configuration register
Alternate function
TIM14_CH1
1. Refer to the AF remap and debug I/O configuration register
configuration register
1. Remap available only for 100-pin and for 144-pin package.
Alternate function
General-purpose and alternate-function I/Os (GPIOs and AFIOs)

Table 30. TIM5 alternate function remapping

TIM5CH4_IREMAP = 0
TIM5 Channel 4 is
connected to PA3

Table 31. TIM12 remapping

(AFIO_MAPR2). Remap available only for high-density value line devices.

Table 32. TIM13 remapping

(AFIO_MAPR2). Remap available only for high-density value line devices.

Table 33. TIM14 remapping

(AFIO_MAPR2). Remap available only for high-density value line devices.

Table 34. TIM4 alternate function remapping

Alternate function
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4

Table 35. TIM3 alternate function remapping

TIM3_REMAP[1:0] =
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
LSI internal clock is connected to TIM5_CH4
input for calibration purpose.
TIM12_REMAP = 0
PC4
PC5
Section 7.4.7: AF remap and debug I/O
TIM13_REMAP = 0
PC8
Section 7.4.7: AF remap and debug I/O
TIM14_REMAP = 0
PC9
Section 7.4.7: AF remap and debug I/O
TIM4_REMAP = 0
PB6
PB7
PB8
PB9
TIM3_REMAP[1:0] =
"00" (no remap) "10" (partial remap)
PA6
PA7
PB0
PB1
RM0041 Rev 6
(1)
TIM5CH4_IREMAP = 1
(1)
TIM12_REMAP = 1
PB12
PB13
(1)
TIM13_REMAP = 1
PB0
(1)
TIM14_REMAP = 1
PB1
TIM4_REMAP = 1
PD12
PD13
PD14
PD15
TIM3_REMAP[1:0] =
"11" (full remap)
PB4 PC6
PB5 PC7
PC8
PC9
(1)
(1)
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