Hdmi-Cec Functional Description; Block Diagram; Prescaler; Figure 276. Hdmi-Cec Block Diagram - ST STM32F100 Series Reference Manual

RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™-
the transmitted message. All CEC devices therefore have both a physical and a logical
address, whereas non-CEC devices only have a physical address.
Once their physical and logical addresses are known, each CEC device transmits them to
all other devices, thus allowing any device to create a map of the network.
24.7

HDMI-CEC functional description

24.7.1

Block diagram

The HDMI-CEC controller handles complete messages but requires the CPU to provide or
unload the data bytes one by one.
Figure 276
CEC Line
1. The timing checker block verifies the received bit timings, while the timing generator controls the
transmitted bit timings.
24.7.2

Prescaler

The prescaler defines the time quantum for the timing checker and timing generator blocks.
Additionally, it provides a time quantum reference for complying with the required signal free
time (SFT). A 14-bit counter is used to provide the necessary 50 microsecond time base,
allowing high APB clocks frequency.
The counter is reset at the beginning of every bit for the timing checker block to operate with
the maximum precision.
Prescaler formula for nominal bit timings is:
shows the CEC controller block diagram.

Figure 276. HDMI-CEC block diagram

Tx/Rx
Timing checker
and generator
Prescaler
Prescaler register
PRESC
RM0041 Rev 6
RX buffer
0 7
Shift register
TX buffer
Control logic
[ 50 × F 〈 MHz 〉 ] 1
= –
APB
Configuration register
Own address register
Control/status register
Error status register
653/709
ai17321
668