ST STM32F100 Series Reference Manual page 14

Contents
15.6.1
15.6.2
15.6.3
15.6.4
15.6.5
15.6.6
15.6.7
15.6.8
15.6.9
15.6.10 TIM16&TIM17 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . 448
15.6.11 TIM16&TIM17 repetition counter register (TIMx_RCR) . . . . . . . . . . . . 449
15.6.12 TIM16&TIM17 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . 449
15.6.13 TIM16&TIM17 break and dead-time register (TIMx_BDTR) . . . . . . . . 450
15.6.14 TIM16&TIM17 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . 451
15.6.15 TIM16&TIM17 DMA address for full transfer (TIMx_DMAR) . . . . . . . . 452
15.6.16 TIM16&TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
16 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.1 TIM6 and TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.2 TIM6 and TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.3 TIM6 and TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . 457
16.3.1
16.3.2
16.3.3
16.3.4
16.4 TIM6 and TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
16.4.1
16.4.2
16.4.3
16.4.4
16.4.5
16.4.6
16.4.7
16.4.8
16.4.9
17 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
14/709
TIM16&TIM17 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . 437
TIM16&TIM17 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . 438
TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 440
TIM16&TIM17 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 441
TIM16&TIM17 event generation register (TIMx_EGR) . . . . . . . . . . . . 442
TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1) . . . 443
TIM16&TIM17 capture/compare enable register (TIMx_CCER) . . . . . 445
TIM16&TIM17 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 448
TIM16&TIM17 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . 448
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
TIM6 and TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 463
TIM6 and TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . 465
TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . 465
TIM6 and TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 466
TIM6 and TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . 466
TIM6 and TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 466
TIM6 and TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 467
TIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 467
TIM6 and TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
RM0041 Rev 6
RM0041