Figure 66. Capture/Compare Channel (Example: Channel 1 Input Stage); Figure 67. Capture/Compare Channel 1 Main Circuit - ST STM32F100 Series Reference Manual

Advanced-control timer (TIM1)

Figure 66. Capture/compare channel (example: channel 1 input stage)

TI1
Filter
f
DTS downcounter
ICF[3:0]
TIMx_CCMR1
The output stage generates an intermediate waveform that is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Read CCR1H
S
read_in_progress
Read CCR1L
R
Input
CC1S[1]
mode
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
232/709
TI1F_Rising
TI1F
Edge
TI1F_Falling
detector
CC1P/CC1NP
TIMx_CCER
TI2F_Rising
(from channel 2)
TI2F_Falling
(from channel 2)

Figure 67. Capture/compare channel 1 main circuit

APB Bus
MCU-peripheral interface
8
Capture/compare preload register
capture_transfer
Capture /compare shadow register
Capture
Counter
RM0041 Rev 6
TI1F_ED
To the slave mode controller
0
TI1FP1
1
TI2FP1
TRC
(from slave mode
controller)
0
CC1S[1:0]
1
8
write_in_progress
Output
compare_transfer
mode
Comparator
CNT>CCR1
CNT=CCR1
RM0041
01
IC1PS
IC1 Divider
10
/1, /2, /4, /8
11
ICPS[1:0]
CC1E
TIMx_CCER
TIMx_CCMR1
MS33115V1
write CCR1H
S
write CCR1L
R
CC1S[1]
CC1S[0]
OC1PE
OC1PE
UEV
TIMx_CCMR1
(from time
base unit)
MS31089V3