Figure 97. Counter Timing Diagram, Internal Clock Divided By 1; Figure 98. Counter Timing Diagram, Internal Clock Divided By 2; Figure 99. Counter Timing Diagram, Internal Clock Divided By 4 - ST STM32F100 Series Reference Manual

General-purpose timers (TIM2 to TIM5)
Timerclock = CK_CNT
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)
Timerclock = CK_CNT
Update event (UEV)
Update interrupt flag (UIF)
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Figure 97. Counter timing diagram, internal clock divided by 1

CK_INT
CNT_EN
Counter register
05

Figure 98. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
Counter register
0002
Counter underflow

Figure 99. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
04 03 02 01 00 36
0001 0000 0036
0001 0000
RM0041 Rev 6
35 34 33 32 31 30 2F
0035 0034 0033
0036
RM0041
MSv37305V1
MSv37306V1
0035
MS40511V1