Tim13/14 Event Generation Register (Timx_Egr); Tim13/14 Capture/Compare Mode Register 1 (Timx_Ccmr1) - ST STM32F100 Series Reference Manual

RM0041
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
14.5.4

TIM13/14 event generation register (TIMx_EGR)

Address offset: 0x14
Reset value: 0x0000
15 14 13
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 CC1G: Capture/compare 1 generation
Bit 0 UG: Update generation
14.5.5

TIM13/14 capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So take care that the same bit can have a
different meaning for the input stage and for the output stage.
15 14 13
– At overflow and if UDIS='0' in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS='0' and UDIS='0' in the TIMx_CR1 register.
12 11 10 9
Reserved
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.
12 11 10 9
Reserved
Reserved
General-purpose timers (TIM12/13/14)
8 7 6
8 7 6
OC1M[2:0]
IC1F[3:0]
rw rw
RM0041 Rev 6
5 4 3 2
5 4 3 2
OC1PE OC1FE
IC1PSC[1:0]
rw rw rw rw
1 0
CC1G UG
w w
1 0
CC1S[1:0]
rw rw
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