Irda Sir Endec Block - ST STM32F100 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
prescaler register USART_GTPR. CK frequency can be programmed from f
where f
CK
23.3.12

IrDA SIR ENDEC block

The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA
mode, the following bits must be kept cleared:
•
LINEN, STOP and CLKEN bits in the USART_CR2 register,
•
SCEN and HDSEL bits in the USART_CR3 register.
The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation
scheme that represents logic 0 as an infrared light pulse (see
The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream
output from USART. The output pulse stream is transmitted to an external output driver and
infrared LED. USART supports only bit rates up to 115.2Kbps for the SIR ENDEC. In normal
mode the transmitted pulse width is specified as 3/16 of a bit period.
The SIR receive decoder demodulates the return-to-zero bit stream from the infrared
detector and outputs the received NRZ serial bit stream to USART. The decoder input is
normally HIGH (marking state) in the Idle state. The transmit encoder output has the
opposite polarity to the decoder input. A start bit is detected when the decoder input is low.
•
IrDA is a half duplex communication protocol. If the Transmitter is busy (i.e. the USART
is sending data to the IrDA encoder), any data on the IrDA receive line is ignored by the
IrDA decoder and if the Receiver is busy (USART is receiving decoded data from the
USART), data on the TX from the USART to IrDA is not encoded by IrDA. While
receiving data, transmission should be avoided as the data to be transmitted could be
corrupted.
•
A '0 is transmitted as a high pulse and a '1 is transmitted as a '0. The width of the pulse
is specified as 3/16th of the selected bit period in normal mode (see
• The SIR decoder converts the IrDA compliant receive signal into a bit stream for
USART.
•
The SIR receive logic interprets a high state as a logic one and low pulses as logic
zeros.
•
The transmit encoder output has the opposite polarity to the decoder input. The SIR
output is in low state when Idle.
• The IrDA specification requires the acceptance of pulses greater than 1.41 us. The
acceptable pulse width is programmable. Glitch detection logic on the receiver end
filters out pulses of width less than 2 PSC periods (PSC is the prescaler value
programmed in the IrDA low-power Baud Register, USART_GTPR). Pulses of width
less than 1 PSC period are always rejected, but those of width greater than one and
less than two periods may be accepted or rejected, those greater than 2 periods are
accepted as a pulse. The IrDA encoder/decoder does not work when PSC = 0.
•
The receiver can communicate with a low-power transmitter.
•
In IrDA mode, the STOP bits in the USART_CR2 register must be configured to "1 stop
bit".
628/709
is the peripheral input clock.
RM0041 Rev 6
RM0041
/2 to f
CK
Figure 260).
Figure 261).
/62,
CK