Figure 217. Asynchronous Wait During A Read Access - ST STM32F100 Series Reference Manual

Flexible static memory controller (FSMC)
1. DATAST in FSMC_BTRx register) Memory asserts the WAIT signal aligned to
NOE/NWE which toggles:
2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then
DATAST
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 217
memory access after WAIT is released by the asynchronous memory (independently of the
above cases).
A[25:0]
NEx
NWAIT
NOE
D[15:0]
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
518/709
≥ (
DATAST 4
max_wait_assertion_time address_phase
(
≥ ( × )
4 HCLK + max_wait_assertion_time
and Figure 218 show the number of HCLK clock cycles that are added to the

Figure 217. Asynchronous wait during a read access

address phase
don't care
RM0041 Rev 6
× )
HCLK + max_wait_assertion_time
>
–
≥ ×
DATAST 4 HCLK
Memory transaction
data setup phase
+ hold_phase
–
address_phase hold_phase
don't care
data driven
by memory
4HCLK
RM0041
)
ai18471b