Lin (Local Interconnection Network) Mode - ST STM32F100 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
Odd parity
The parity bit is calculated to obtain an odd number of "1s" inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit in
USART_CR1 = 1).
Parity checking in reception
If the parity check fails, the PE flag is set in the USART_SR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software
sequence (a read from the status register followed by a read or write access to the
USART_DR data register).
Note: In case of wakeup by an address mark: the MSB bit of the data is taken into account to
identify an address but not the parity bit. And the receiver does not check the parity of the
address data (PE is not set in case of a parity error).
Parity generation in transmission
If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register
is transmitted but is changed by the parity bit (even number of "1s" if even parity is selected
(PS=0) or an odd number of "1s" if odd parity is selected (PS=1)).
Note: The software routine that manages the transmission can activate the software sequence
which clears the PE flag (a read from the status register followed by a read or write access
to the data register). When operating in half-duplex mode, depending on the software, this
can cause the PE flag to be unexpectedly cleared.
23.3.8

LIN (local interconnection network) mode

The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN
mode, the following bits must be kept cleared:
• STOP[1:0] and CLKEN in the USART_CR2 register
•
SCEN, HDSEL and IREN in the USART_CR3 register.
LIN transmission
The same procedure explained in
transmission than for normal USART transmission with the following differences:
•
Clear the M bit to configure 8-bit word length.
•
Set the LINEN bit to enter LIN mode. In this case, setting the SBK bit sends 13 '0 bits
as a break character. Then a bit of value '1 is sent to allow the next start detection.
LIN reception
A break detection circuit is implemented on the USART interface. The detection is totally
independent from the normal USART receiver. A break can be detected whenever it occurs,
during Idle state or during a frame.
When the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a
start signal. The method for detecting start bits is the same when searching break
characters or data. After a start bit has been detected, the circuit samples the next bits
exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in
USART_CR2) or 11 (when LBDL=1 in USART_CR2) consecutive bits are detected as '0,
620/709
Section 23.3.2 has to be applied for LIN Master
RM0041 Rev 6
RM0041