Flexible Static Memory Controller (Fsmc); Fsmc Main Features - ST STM32F100 Series Reference Manual

Flexible static memory controller (FSMC)

20 Flexible static memory controller (FSMC)
Low-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 16 and 32 Kbytes.
Medium-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 64 and 128 Kbytes.
High-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 256 and 512 Kbytes.
This section applies to high-density value line devices only.
20.1

FSMC main features

The FSMC block is able to interface with synchronous and asynchronous memories
. Its main purpose is to:
•
Translate the AHB transactions into the appropriate external device protocol
•
Meet the access timing requirements of the external devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique chip select. The FSMC performs
only one access at a time to an external device.
The FSMC has the following main features:
• Interfaces with static memory-mapped devices including:
–
–
–
• Supports burst mode access to synchronous devices (NOR flash and PSRAM)
•
8- or 16-bit wide databus
• Independent chip select control for each memory bank
•
Independent configuration for each memory bank
• Programmable timings to support a wide range of devices, in particular:
–
–
–
–
•
Write enable and byte lane select outputs for use with PSRAM and SRAM devices
• Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to
external 16-bit or 8-bit devices
•
A Write FIFO, 2-word long , each word is 32 bits wide, only stores data and not the
address. Therefore, this FIFO only buffers AHB write burst transactions. This makes it
possible to write to slow memories and free the AHB quickly for other operations. Only
one burst at a time is buffered: if a new AHB burst or single transaction occurs while an
494/709
Static random access memory (SRAM)
NOR/OneNAND flash memory
PSRAM (4 memory banks)
Programmable wait states (up to 15)
Programmable bus turnaround cycles (up to 15)
Programmable output enable and write enable delays (up to 15)
Independent read and write timings and protocol, so as to support the widest
variety of memories and timings
RM0041 Rev 6
RM0041