Rcc Register Map; Table 21. Rcc Register Map And Reset Values - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus
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Reset and clock control (RCC)
6.3.28

RCC register map

Table 21
Addr.
Register
offset
name
RCC_CR
0x00
Reset value
RCC_PLL
CFGR
0x04
Reset value
MCO
RCC_CFGR
2
0x08
[1:0]
Reset value
0
RCC_CIR
0x0C
Reset value
RCC_AHB1
RSTR
0x10
Reset value
RCC_AHB2
RSTR
0x14
Reset value
RCC_AHB3
RSTR
0x18
Reset value
Reserved
0x1C
Reset value
RCC_APB1
RSTR
0x20
Reset value
172/1328
gives the register map and reset values.

Table 21. RCC register map and reset values

0
0
0
0
0
0
PLLR
PLLQ[3:0]
[2:0]
0
1
0
0
1
0
0
MCO2
MCO1
PRE
PRE
[2:0]
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
PLLP
[1:0]
0
0
0
MCO
PPRE2
1
RTCPRE[4:0]
[2:0]
[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0390 Rev 4
HSICAL[7:0]
HSITRIM[4:0]
x
x
x
x
x
x
x
1
PLLN[8:0]
0
1
1
0
0
0
0
0
PPRE1
HPRE[3:0]
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0390
0
0
0
0
1
1
PLLM[5:0]
0
0
1
0
0
0
0
SWS
SW
[1:0]
[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

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