Reference Arm® Documentation; Swj Debug Port (Serial Wire And Jtag); Figure 285. Swj Debug Port - ST STM32F100 Series Reference Manual

RM0041
25.2 Reference Arm
• Cortex
It is available from:
http://infocenter.arm.com/
•
Arm
• Arm
25.3

SWJ debug port (serial wire and JTAG)

The core of the STM32F100xx integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is
®
an Arm
SW-DP (2-pin) interface.
•
The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
•
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
Figure 285
TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP.
®
documentation
®
-M3 r1p1 Technical Reference Manual (TRM)
®
Debug Interface V5
®
CoreSight Design Kit revision r1p1 Technical Reference Manual
standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a
shows that the asynchronous TRACE output (TRACESWO) is multiplexed with

Figure 285. SWJ debug port

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