Figure 260. Irda Sir Endec- Block Diagram; Figure 261. Irda Data Modulation (3/16) -Normal Mode - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32F100 Series:

Table of Contents

IrDA low-power mode

Transmitter:

In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the

width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz.

Generally this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode

programmable divisor divides the system clock to achieve this value.

Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the

USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if

its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in

USART_GTPR).

A pulse of width less than two and greater than one PSC period(s) may or may not be

The receiver set up time should be managed by software. The IrDA physical layer

specification specifies a minimum of 10 ms delay between transmission and reception (IrDA

is a half duplex protocol).

Universal synchronous asynchronous receiver transmitter (USART)

Figure 260. IrDA SIR ENDEC- block diagram

RM0041 Rev 6

Do you have a question about the STM32F100 Series and is the answer not in the manual?