ST STM32F100 Series Reference Manual page 485

Advanced arm-based 32-bit mcus

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Bits 31:2 Reserved, must be kept at reset value.

Bit 1 RVU: Watchdog counter reload value update

Bit 0 PVU: Watchdog prescaler value update

If several reload values or prescaler values are used by application, it is mandatory to wait

until RVU bit is reset before changing the reload value and to wait until PVU bit is reset

before changing the prescaler value. However, after updating the prescaler and/or the

reload value it is not necessary to wait until RVU or PVU is reset before continuing code

execution (even in case of low-power mode entry, the write operation is taken into account

and completes)

This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset

by hardware when the reload value update operation is completed in the V

(takes up to 5 RC 40 kHz cycles).

Reload value can be updated only when RVU bit is reset.

This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is

reset by hardware when the prescaler update operation is completed in the V

domain (takes up to 5 RC 40 kHz cycles).

Prescaler value can be updated only when PVU bit is reset.

RM0041 Rev 6

Independent watchdog (IWDG)

voltage domain

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