Tim15 Dma Control Register (Tim15_Dcr) - ST STM32F100 Series Reference Manual

RM0041
Bit 10 OSSI: Off-state selection for Idle mode
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
Bits 9:8 LOCK[1:0]: Lock configuration
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
Bits 7:0 DTG[7:0]: Dead-time generator setup
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
15.5.16

TIM15 DMA control register (TIM15_DCR)

Address offset: 0x48
Reset value: 0x0000
15 14 13
Reserved
Res.
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details
enable register (TIM15_CCER) on page
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
bits in TIMx_BDTR register).
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as well
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
has been written, their content is frozen until the next reset.
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x t
DTG[7:5]=10x => DT=(64+DTG[5:0])xt
DTG[7:5]=110 => DT=(32+DTG[4:0])xt
DTG[7:5]=111 => DT=(32+DTG[4:0])xt
Example if T =125ns (8MHz), dead-time possible values are:
DTS
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
(LOCK bits in TIMx_BDTR register).
12 11 10 9
DBL[4:0]
rw rw rw rw
General-purpose timers (TIM15/16/17)
(Section 15.5.8: TIM15 capture/compare
426).
with t =t
dtg dtg DTS
with T =2xt
dtg dtg
with T =8xt
dtg dtg
with T =16xt
dtg dtg
8 7 6
Reserved
rw Res.
RM0041 Rev 6
DTS
DTS
DTS
5 4 3 2
DBA[4:0]
rw rw rw
1 0
rw rw
433/709
455