Mcu Debug Component (Dbgmcu); Debug Support For Low-Power Modes; Debug Support For Timers, Watchdog And I; 688 - ST STM32F100 Series Reference Manual

Debug support (DBG)
Example of configuration
To output a simple value to the TPIU:
•
Configure the TPIU and assign TRACE I/Os by configuring the DBGMCU_CR (refer to
Section 25.16.2
•
Write 0xC5ACCE55 to the ITM Lock Access register to unlock the write access to the
ITM registers
•
Write 0x00010005 to the ITM Trace Control register to enable the ITM with Sync
enabled and an ATB ID different from 0x00
•
Write 0x1 to the ITM Trace Enable register to enable the Stimulus Port 0
•
Write 0x1 to the ITM Trace Privilege register to unmask stimulus ports 7:0
•
Write the value to output in the Stimulus Port register 0: this can be done by software
(using a printf function)
25.15

MCU debug component (DBGMCU)

The MCU debug component helps the debugger provide support for:
•
Low-power modes
•
Clock control for timers, watchdog, I2C during a breakpoint
•
Control of the trace pins assignment
25.15.1

Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
•
In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by
the debugger. This feeds HCLK with the same clock that is provided to FCLK (system
clock previously configured by the software).
•
In Stop mode, the bit DBG_STOP must be previously set by the debugger. This
enables the internal RC oscillator clock to feed FCLK and HCLK in STOP mode.
25.15.2

Debug support for timers, watchdog and I

During a breakpoint, it is necessary to choose how the counter of timers and watchdog must
behave:
•
They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
•
They can stop to count inside a breakpoint. This is required for watchdog purposes.
2
For the I

688/709

and Section
C, the user can choose to block the SMBUS timeout during a breakpoint.
25.15.3)
2
RM0041 Rev 6
C
RM0041