ST STM32F100 Series Reference Manual page 527

RM0041
Bit 14 EXTMOD: Extended mode enable.
Bit 13 WAITEN: Wait enable bit.
Bit 12 WREN: Write enable bit.
Bit 11 WAITCFG: Wait timing configuration.
Bit 10 WRAPMOD: Wrapped burst mode support.
Bit 9 WAITPOL: Wait signal polarity bit.
Bit 8 BURSTEN: Burst enable bit.
This bit enables the FSMC to program the write timings for non-multiplexed
asynchronous accesses inside the FSMC_BWTR register, thus resulting in different
timings for read and write operations.
0: values inside FSMC_BWTR register are not taken into account (default after reset)
1: values inside FSMC_BWTR register are taken into account
Note: When the extended mode is disabled, the FSMC can operate in Mode1 or Mode2
as follows:
– Mode 1 is the default mode when the SRAM/PSRAM memory type is selected
(MTYP [0:1]=0x0 or 0x01)
– Mode 2 is the default mode when the NOR memory type is selected
(MTYP [0:1]= 0x10).
This bit enables/disables wait-state insertion via the NWAIT signal when accessing the
flash memory in synchronous mode.
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after
the programmed flash latency period)
1: NWAIT signal is enabled (its level is taken into account after the programmed flash
latency period to insert wait states if asserted) (default after reset)
This bit indicates whether write operations are enabled/disabled in the bank by the
FSMC:
0: Write operations are disabled in the bank by the FSMC, an AHB error is reported,
1: Write operations are enabled for the bank by the FSMC (default after reset).
The NWAIT signal indicates whether the data from the memory are valid or if a wait state
must be inserted when accessing the flash memory in synchronous mode. This
configuration bit determines if NWAIT is asserted by the memory one clock cycle before
the wait state or during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset),
1: NWAIT signal is active during wait state (not used for PRAM).
Defines whether the controller splits or not an AHB burst wrap access into two linear
accesses. Valid only when accessing memories in burst mode
0: Direct wrapped burst is not enabled (default after reset),
1: Direct wrapped burst is enabled.
Note: This bit has no effect as the CPU and DMA cannot generate wrapping burst
transfers.
Defines the polarity of the wait signal from memory. Valid only when accessing the
memory in burst mode:
0: NWAIT active low (default after reset),
1: NWAIT active high.
This bit enables/disables synchronous accesses during read operations. It is valid only
for synchronous memories operating in burst mode:
0: Burst mode disabled (default after reset). Read accesses are performed in
asynchronous mode.
1: Burst mode enable. Read accesses are performed in synchronous mode.
RM0041 Rev 6
Flexible static memory controller (FSMC)
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