Figure 233. I2C Bus Protocol - ST STM32F100 Series Reference Manual

Inter-integrated circuit (I2C) interface
Communication flow
In Master mode, the I
serial data transfer always begins with a start condition and ends with a stop condition. Both
start and stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection may be enabled or disabled
by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to
SDA
SCL
Acknowledge may be enabled or disabled by software. The I
addressing 7-bit/ 10-bit and/or general call address) can be selected by software.
The block diagram of the I
568/709
2
C interface initiates a data transfer and generates the clock signal. A
Figure 233. I
MSB
1
Start
condition
2
C interface is shown in
RM0041 Rev 6
Figure
2
C bus protocol
2 8
Figure
233.
ACK
9
Stop
condition
2
C interface addresses (dual
234.
RM0041
MS19854V1