Figure 56. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 57. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F100 Series Reference Manual

RM0041 Advanced-control timer (TIM1)

Figure 56. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC
CNT_EN
Timerclock = CK_CNT
0034 0035 0036 0035
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31191V2
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 57. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
Counter register
20 1F 01 00
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
MS31192V2
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