Figure 8. Stm32F100Xx Clock Tree (Low And Medium-Density Devices) - ST STM32F100 Series Reference Manual

RM0041
The devices have the following two secondary clock sources:
•
40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
•
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
MCO
1. For full details about the internal and external clock source characteristics, refer to the "Electrical
characteristics" section in the device datasheet.

Figure 8. STM32F100xx clock tree (low and medium-density devices)

8 MHz
HSI
HSI RC
/2
PLLSRC
PLLMUL
..., x16
x2, x3, x4
PLL
PREDIV1
/1/2/3.../
.../15/16
4-24 MHz
HSE OSC
/128
LSE OSC LSE
32.768 kHz
RTCSEL[1:0]
LSI RC LSI
40 kHz
Main
/2
cloc k out put
MCO
FLITFCLK
to Flash programming interface
SW
HSI
AHB
SYSCLK
Prescaler
PLLCLK 24 MHz
/1, 2..512
max
HSE
CSS
to RTC
RTCCLK
to independent watchdog (IWDG)
IWDGCLK
PLLCLK
HSI
HSE
SYSCLK
RM0041 Rev 6
Reset and clock control (RCC)
HCLK
24 MHz max
to AHB bus, core,
memory and DMA
Clock
Enable
to Cortex System timer
/8
FCLK Cortex
free running clock
APB1
24 MHz max
Prescaler
/1, 2, 4, 8, 16
Peripheral Clock
Enable
TIM2,3,4,6,7
to TIM2,3,4,6 and 7
If (APB1 prescaler =1) x1
else x2
Peripheral Clock
Enable
APB2
24 MHz max
Prescaler
/1, 2, 4, 8, 16
Peripheral Clock
Enable
to TIM1, TIM15,
TIM1/15/16/17 timers
TIM16 and TIM17
If (APB2 prescaler =1) x1
TIMxCLK
else x2
Peripheral Clock
Enable
ADC
Prescaler
ADCCLK 12 MHz max
/2, 4, 6, 8
Legend:
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low -speed external clock signal
PCLK1
to APB1
peripherals
TIMxCLK
PCLK2
peripherals to APB2
to ADC1
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