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RM0041
FSMC signal name
NBL[1]
NBL[0]
PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
20.5.2
Supported memories and transactions
Table 97
transactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM.
Transactions not allowed (or not supported) by the FSMC in this example appear in gray.
Table 97. NOR flash/PSRAM controller: example of supported memories and transactions
Device
Asynchronous
Asynchronous
Asynchronous
Asynchronous
NOR flash
Asynchronous
(muxed I/Os and
Asynchronous
nonmuxed I/Os)
Asynchronous page
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
PSRAM
Asynchronous
(multiplexed and
nonmultiplexed
Asynchronous page
I/Os)
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Table 96. Multiplexed I/O PSRAM (continued)
I/O
O
Upper byte enable (memory signal name: NUB)
O
Lowed byte enable (memory signal name: NLB)
below displays an example of the supported devices, access modes and
Mode
R/W
R
W
R
W
R
W
R
R
R
R
R
W
R
W
R
W
R
R
R
R
W
W
Flexible static memory controller (FSMC)
AHB
Allowed/
Memory
data
data size
size
allowed
8
16
8
16
16
16
16
16
32
16
32
16
-
16
8
16
16
16
32
16
8
16
8
16
16
16
16
16
32
16
32
16
-
16
8
16
16
16
32
16
8
16
16 / 32
16
RM0041 Rev 6
Function
not
Comments
Y
-
N
-
Y
-
Y
-
Y
Split into two FSMC accesses
Y
Split into two FSMC accesses
N
Mode is not supported
N
-
Y
-
Y
-
Y
-
Y
Use of byte lanes NBL[1:0]
Y
-
Y
-
Y
Split into two FSMC accesses
Y
Split into two FSMC accesses
N
Mode is not supported
N
-
Y
-
Y
-
Y
Use of byte lanes NBL[1:0]
Y
-
501/709
535
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