Figure 153. Example Of One Pulse Mode - ST STM32F100 Series Reference Manual

RM0041
For example the user may want to generate a positive pulse on OC1 with a length of t
and after a delay of t
Use TI2FP2 as trigger 1:
1. Map TI2FP2 to TI2 by writing CC2S='01' in the TIMx_CCMR1 register.
2. TI2FP2 must detect a rising edge, write CC2P='0' and CC2NP = '0' in the TIMx_CCER
register.
3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS='110' in
the TIMx_SMCR register.
4. TI2FP2 is used to start the counter by writing SMS to '110' in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
•
The t
•
The t
value (TIMx_ARR - TIMx_CCR1).
•
Let us say the user wants to build a waveform with a transition from '0' to '1' when a
compare match occurs and a transition from '1' to '0' when the counter reaches the
auto-reload value. To do this enable PWM mode 2 by writing OC1M='111' in the
TIMx_CCMR1 register. The user can optionally enable the preload registers by writing
OC1PE='1' in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case the user has to write the compare value in the TIMx_CCR1 register, the auto-
reload value in the TIMx_ARR register, generate an update by setting the UG bit and
wait for external trigger event on TI2. CC1P is written to '0' in this example.
The user only wants one pulse (Single mode), so write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive mode is selected.

Figure 153. Example of one pulse mode.

TI2
OC1REF
OC1
TIM1_ARR
TIM1_CCR1
0
as soon as a positive edge is detected on the TI2 input pin.
DELAY
is defined by the value written in the TIMx_CCR1 register.
DELAY
is defined by the difference between the auto-reload value and the compare
PULSE
General-purpose timers (TIM12/13/14)
t
t
DELAY PULSE
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t
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PULSE
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