Timer Synchronization; Debug Mode; Tim15 Registers; Figure 185. Control Circuit In Trigger Mode - ST STM32F100 Series Reference Manual

RM0041
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
• Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don't need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so no need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register.
Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level
only).
•
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
15.4.15

Timer synchronization

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 13.3.15: Timer synchronization on page 316
Note: The clock of the slave timer must be enabled prior to receiving events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
15.4.16

Debug mode

When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to
watchdog and I
15.5

TIM15 registers

Refer to
register descriptions.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

Figure 185. Control circuit in trigger mode

cnt_en
Counter clock = ck_cnt = ck_psc
Counter register
2
C.
Section 1.1: List of abbreviations for registers
General-purpose timers (TIM15/16/17)
TI2
34
TIF
Section 25.15.2: Debug support for timers,
RM0041 Rev 6
35 36 37 38
for details.
®
-M3 core halted), the TIMx counter
for a list of abbreviations used in
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