Repetition Counter; Figure 58. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow); Figure 59. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - ST STM32F100 Series Reference Manual

Advanced-control timer (TIM1)

Figure 58. Counter timing diagram, update event with ARPE=1 (counter underflow)

Figure 59. Counter timing diagram, Update event with ARPE=1 (counter overflow)

Timer clock = CK_CNT
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload active register
12.3.3

Repetition counter

Section 12.3.1: Time-base unit
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N+1 counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
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CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
CK_PSC
CEN
Counter register
Counter overflow
Update event (UEV)
Write a new value in TIMx_ARR
06 05 04 03 02
FD
FD
F7 F8 F9 FA FB FC 36
FD
FD
describes how the update event (UEV) is generated with
RM0041 Rev 6
01 00 01 02 03 04 05 06 07
36
36
35 34 33 32 31 30 2F
36
36
RM0041
MS31193V3
MS31194V2