External Interrupt Configuration Register 3 (Afio_Exticr3); External Interrupt Configuration Register 4 (Afio_Exticr4) - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0041
7.4.5

External interrupt configuration register 3 (AFIO_EXTICR3)

Address offset: 0x10
Reset value: 0x0000
31
30
29
15
14
13
EXTI11[3:0]
rw
rw
rw
Bits 31:16
Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
7.4.6

External interrupt configuration register 4 (AFIO_EXTICR4)

Address offset: 0x14
Reset value: 0x0000
31
30
29
15
14
13
EXTI15[3:0]
rw
rw
rw
Bits 31:16
Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
28
27
26
25
12
11
10
9
EXTI10[3:0]
rw
rw
rw
rw
28
27
26
25
12
11
10
9
EXTI14[3:0]
rw
rw
rw
rw
24
23
22
Reserved
8
7
6
EXTI9[3:0]
rw
rw
rw
24
23
22
Reserved
8
7
6
EXTI13[3:0]
rw
rw
rw
RM0041 Rev 6
21
20
19
18
5
4
3
2
EXTI8[3:0]
rw
rw
rw
rw
21
20
19
18
5
4
3
2
EXTI12[3:0]
rw
rw
rw
rw
17
16
1
0
rw
rw
17
16
1
0
rw
rw
127/709
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