Figure 2. High Density Value Line System Architecture - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus

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In high-density value line devices, the main system consists of:

Four masters:

Four slaves:

These are interconnected using a multilayer AHB bus architecture as shown in

This bus connects the instruction bus of the Cortex

instruction interface. Instruction fetches are performed on this bus.

This bus connects the DCode bus (literal load and debug access) of the Cortex

the flash memory data interface.

-M3 core DCode bus (D-bus) and System bus (S-bus)

GP-DMA1 & 2 (general-purpose DMA)

Internal SRAM

Internal flash memory

AHB to APB bridges (AHB to APBx), which connect all the APB peripherals

Figure 2. High density value line system architecture

AHB system bus

Reset & clock

control (RCC)

-M3 core to the flash memory

RM0041 Rev 6

Memory and bus architecture

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