Table 114. Fsmc_Bcrx Bit Fields; Figure 220. Synchronous Multiplexed Read Mode - Nor, Psram (Cram) - ST STM32F100 Series Reference Manual

Flexible static memory controller (FSMC)

Figure 220. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)

(WAITCFG=
A/D[15:0]
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access,
they are held low.
2. NWAIT polarity is set to 0.
Bit No.
31-20
19
18-16
15
14
13
12
11
10
9
8
7
6
5-4
522/709
HCLK
CLK
A[25:16] addr[25:16]
NEx
NOE
High
NWE
NADV
NWAIT
0)
Addr[15:0]
1 clock 1 clock
cycle cycle

Table 114. FSMC_BCRx bit fields

Bit name
Reserved 0x000
CBURSTRW No effect on synchronous read
CPSIZE As needed (0x1 for CRAM 1.5)
ASCYCWAIT 0x0
EXTMOD 0x0
WAITEN Set to 1 if the memory supports this feature, otherwise keep at 0.
WREN no effect on synchronous read
WAITCFG to be set according to memory
WRAPMOD 0x0
WAITPOL to be set according to memory
BURSTEN 0x1
Reserved 0x1
FACCEN Set according to memory support (NOR flash memory)
MWID As needed
Memory transaction = burst of 4 half words
(DATLAT + 2)
CLK cycles
data data
Data strobes
RM0041 Rev 6
inserted wait state
data data
Data strobes
Value to set
RM0041
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