Rtc Register Map; Table 85. Rtc Register Map And Reset Values - ST STM32F100 Series Reference Manual

Real-time clock (RTC)
17.4.7

RTC register map

RTC registers are mapped as 16-bit addressable registers as described in the table below:
Offset Register
RTC_CRH
0x00
Reset value
RTC_CRL
0x04
Reset value
RTC_PRLH
0x08
Reset value
RTC_PRLL
0x0C
Reset value
RTC_DIVH
0x10
Reset value
RTC_DIVL
0x14
Reset value
RTC_CNTH
0x18
Reset value
RTC_CNTL
0x1C
Reset value
RTC_ALRH
0x20
Reset value
RTC_ALRL
0x24
Reset value
Refer to
High-density device register boundary addresses
480/709
RTC
Table 85.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 1: Low and medium-density device register boundary addresses
register map and reset values
Reserved
Reserved
Reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
for the register boundary addresses.
RM0041 Rev 6
RM0041
0 0 0
1 0 0 0 0 0
PRL[19:16]
0 0 0 0
PRL[15:0]
DIV[31:16]
DIV[15:0]
CNT[13:16]
CNT[15:0]
ALR[31:16]
ALR[15:0]
and Table 2: