Cec Error Status Register (Cec_Esr) - ST STM32F100 Series Reference Manual

RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™-
24.9.4

CEC error status register (CEC_ESR)

CEC_ESR is the CEC error status register. It contains all the error flags related to the
communication.
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:7 Reserved, must be kept cleared.
Bit 6 TBTFE: Tx block transfer finished error
This bit is set by hardware when the TBTRF bit is not cleared while the requested byte needs
to be transmitted.
It is cleared by software when clearing the TX error flag (TERR) of the CEC_CSR register.
Bit 5 LINE: Line error
This bit is set by hardware when the CEC line is detected low although it is driven to high
impedance while not in the arbitration phase or during the ACK bit.
It is cleared by software by clearing the TX error flag (TERR) in the CEC_CSR register.
Bit 4 ACKE: Block acknowledge error
This bit is set by hardware when a directly addressed message block is not acknowledged or
when a broadcast message block is negatively acknowledged.
It is cleared by software when clearing the TX error flag (TERR) or the Rx error flag (RERR) in
the CEC_CSR register.
Bit 3 SBE: Start bit error
This bit is set by hardware when the start bit (identified by its low duration only, that is, an error
bit), is detected before the end of a message.
It is cleared by software by clearing the Rx error flag (RERR) in the CEC_CSR register.
Bit 2 RTBFE: Rx block transfer finished error
This bit is set by hardware when the RBTF bit is not cleared while a new byte is ready to be
written to the RX buffer.
It is cleared by software by clearing the Rx error flag (RERR) in the CEC_CSR register.
Bit 1 BPE: Bit period error
This bit is set by hardware when the time between two falling edges on the CEC line is too
short in Bit period error mode or out of specification in Safe mode, start bit excepted. It is not
set if BTE was previously set.
It is cleared by software by clearing the Rx error flag (RERR) in the CEC_CSR register.
Bit 0 BTE: Bit timing error
This bit is set by hardware when an incorrect rising edge position is detected on the CEC line
while in Safe mode, start bit excepted.
It is cleared by software by clearing the Rx error flag (RERR) in the CEC_CSR register.
27 26 25 24
11 10 9
Reserved
RM0041 Rev 6
23 22 21
Reserved
8 7 6
TBTFE LINE
r
20 19 18
5 4 3 2
ACKE SBE RBTFE
r r r r
17 16
1 0
BPE BTE
r r
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