Sw Debug Port; Sw Protocol Introduction; Sw Protocol Sequence; Table 149. Packet Request (8-Bits) - ST STM32F100 Series Reference Manual

Debug support (DBG)
25.8

SW debug port

25.8.1

SW protocol introduction

This synchronous serial protocol uses two pins:
•
SWCLK: clock from host to target
•
SWDIO: bidirectional
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 KΩ
recommended by Arm
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.
25.8.2

SW protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target
Bit
0
1
2
4:3
5
6
7
Refer to the Cortex
registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.
680/709
®
).

Table 149. Packet request (8-bits)

Name
Start Must be "1"
0: DP Access
APnDP
1: AP Access
0: Write Request
RnW
1: Read Request
A[3:2] Address field of the DP or AP registers (refer to
Parity Single bit parity of preceding bits
Stop 0
Not driven by the host. Must be read as "1" by the target because of
Park
the pull-up
®
-M3 r1p1 TRM for a detailed description of DPACC and APACC
RM0041 Rev 6
Description
Table
RM0041
148)