Tim15 Capture/Compare Enable Register (Tim15_Ccer) - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM15/16/17)

Bits 7:4 IC1F[3:0]: Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter

applied to TI1. The digital filter is made of an event counter in which N consecutive events

are needed to validate a transition on the output:

0000: No filter, sampling is done at f

Bits 3:2 IC1PSC: Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).

The prescaler is reset as soon as CC1E='0' (TIMx_CCER register).

00: no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S: Capture/Compare 1 Selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if

an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).

TIM15 capture/compare enable register (TIM15_CCER)

Address offset: 0x20

Reset value: 0x0000

Bit 7 CC2NP: Capture/Compare 2 complementary output polarity

Bit 6 Reserved, must be kept at reset value.

Bit 5 CC2P: Capture/Compare 2 output polarity

Reserved, must be kept at reset value.

refer to CC1NP description

refer to CC1P description

RM0041 Rev 6

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