Core Debug; Table 154. Core Debug Registers - ST STM32F100 Series Reference Manual

Debug support (DBG)
25.10

Core debug

Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can
access these registers directly over the internal Private Peripheral Bus (PPB).
It consists of 4 registers:
Register
DHCSR
DCRSR
DCRDR
DEMCR
Note: Important: these registers are not reset by a system reset. They are only reset by a power-
on reset.
Refer to the Cortex
To Halt on reset, it is necessary to:
•
enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control register
•
enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status register.
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Table 154. Core debug registers

The 32-bit Debug Halting Control and Status register
This provides status information about the state of the processor enable core debug
halt and step the processor
The 17-bit Debug Core register Selector register:
This selects the processor register to transfer data to or from.
The 32-bit Debug Core register Data register:
This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.
The 32-bit Debug Exception and Monitor Control register:
This provides Vector Catching and Debug Monitor Control. This register contains a
bit named TRCENA which enable the use of a TRACE.
®
-M3 r1p1 TRM for further details.
RM0041 Rev 6
Description
RM0041