Scan Mode; Injected Channel Management - ST STM32F100 Series Reference Manual

RM0041
Channels to be guarded by analog
All regular and injected channels
(1)
Single
(1)
Single
(1)
Single
1. Selected by AWDCH[4:0] bits
10.3.8

Scan mode

This mode is used to scan a group of analog channels.
Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit
is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular
channels) or in the ADC_JSQR (for injected channels). A single conversion is performed for
each channel of the group. After each end of conversion the next channel of the group is
converted automatically. If the CONT bit is set, conversion does not stop at the last selected
group channel but continues again from the first selected group channel.
When using scan mode, DMA bit must be set and the direct memory access controller is
used to transfer the converted data of regular group channels to SRAM after each update of
the ADC_DR register.
The injected channel converted data is always stored in the ADC_JDRx registers.
10.3.9

Injected channel management

Triggered injection
To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the
ADC_CR1 register.
1. Start conversion of a group of regular channels either by external trigger or by setting
the ADON bit in the ADC_CR2 register.
2. If an external injected trigger occurs during the regular group channel conversion, the
current conversion is reset and the injected channel sequence is converted in Scan
once mode.
3. Then, the regular group channel conversion is resumed from the last interrupted
regular conversion. If a regular event occurs during an injected conversion, it doesn't
interrupt it but the regular sequence is executed at the end of the injected sequence.
Figure 27
Note: When using triggered injection, the interval between trigger events must be longer than the
injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is two
conversions with a 1.5 clock-period sampling time), the minimum interval between triggers
must be 29 ADC clock cycles.
Table 58. Analog watchdog channel selection (continued)
watchdog
injected channel
regular channel
regular or injected channel
shows the timing diagram.
ADC_CR1 register control bits (x = don't care)
AWDSGL bit
0
1
1
1
RM0041 Rev 6
Analog-to-digital converter (ADC)
AWDEN bit JAWDEN bit
1
0
1
1
1
1
0
1
167/709
189