Jtag/Swd Alternate Function Remapping; Timer Alternate Function Remapping; Table 28. Debug Interface Signals; Table 29. Debug Port Mapping - ST STM32F100 Series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
7.3.3

JTAG/SWD alternate function remapping

The debug interface signals are mapped on the GPIO ports as shown in
To optimize the number of free GPIOs during debugging, this mapping can be configured in
different ways by programming the SWJ_CFG[1:0] bits in the
configuration register
SWJ _CFG
[2:0]
000
001
010
100
Other
1. Released only if not using asynchronous trace.
7.3.4

Timer alternate function remapping

Timer 4 channels 1 to 4 can be remapped from Port B to Port D. Other timer remapping
possibilities are listed in
configuration register
118/709

Table 28. Debug interface signals

Alternate function
JTMS / SWDIO
JTCK / SWCLK
JTDI
JTDO / TRACESWO
NJTRST
TRACECK
TRACED0
TRACED1
TRACED2
TRACED3
(AFIO_MAPR). Refer to

Table 29. Debug port mapping

Available debug ports
Full SWJ (JTAG-DP + SW-DP)
(Reset state)
Full SWJ (JTAG-DP + SW-DP)
but without NJTRST
JTAG-DP Disabled and
SW-DP Enabled
JTAG-DP Disabled and
SW-DP Disabled
Forbidden
Table 35
(AFIO_MAPR).
Table 29.
PA13 / PA14 /
JTMS/ JTCK/S
SWDIO WCLK
X
X
X
Free Free
-
to Table 37. Refer to
RM0041 Rev 6
Table
GPIO port
PA13
PA14
PA15
PB3
PB4
PE2
PE3
PE4
PE5
PE6
AF remap and debug I/O
SWJ I/O pin assigned
PB3 / JTDO/
PA15 /
TRACE
JTDI
SWO
X X X
X X x
X Free Free
Free Free
- - -
AF remap and debug I/O
RM0041
28.
PB4/
NJTRST
X
Free
(1)
Free
Free
-