Error Management; Interrupts; Dma Request Mapping; Table 53. Dma Interrupt Requests - ST STM32F100 Series Reference Manual

Direct memory access controller (DMA)
and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two
examples below:
•
To write the halfword "0xABCD", the DMA sets the HWDATA bus to "0xABCDABCD"
with HSIZE = HalfWord
• To write the byte "0xAB", the DMA sets the HWDATA bus to "0xABABABAB" with
HSIZE = Byte
Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the
HSIZE data into account, it transforms any AHB byte or halfword operation into a 32-bit APB
operation in the following manner:
•
an AHB byte write operation of the data "0xB0" to 0x0 (or to 0x1, 0x2 or 0x3) is
converted to an APB word write operation of the data "0xB0B0B0B0" to 0x0
•
an AHB halfword write operation of the data "0xB1B0" to 0x0 (or to 0x2) is converted to
an APB word write operation of the data "0xB1B0B1B0" to 0x0
For instance, to write the APB backup registers (16-bit registers aligned to a 32-bit address
boundary), the memory source size (MSIZE) must be configured to "16-bit" and the
peripheral destination size (PSIZE) to "32-bit".
9.3.5

Error management

A DMA transfer error can be generated by reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or a write access, the faulty
channel is automatically disabled through a hardware clear of its EN bit in the corresponding
Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag
(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error
interrupt enable bit (TEIE) in the DMA_CCRx register is set.
9.3.6

Interrupts

An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for
each DMA channel. Separate interrupt enable bits are available for flexibility.
Half-transfer
Transfer complete
Transfer error
Note: In high-density value line devices, DMA2 Channel4 and DMA2 Channel5 interrupts are
mapped onto the same interrupt vector. All other DMA1 and DMA2 Channel interrupts have
their own interrupt vector.
9.3.7

DMA request mapping

DMA1 controller
The 7 requests from the peripherals (TIMx[1,2,3,4,6,7,15,16,17], ADC1, SPI[1,2], I2Cx[1,2],
USARTx[1,2,3]) and DAC Channelx[1,2] are simply logically ORed before entering the
DMA1, this means that only one request must be enabled at a time. Refer to
150/709

Table 53. DMA interrupt requests

Interrupt event
RM0041 Rev 6
Event flag Enable Control bit
HTIF
TCIF
TEIF
RM0041
HTIE
TCIE
TEIE
Figure 22.