Timer Synchronization (Tim12); Debug Mode - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus

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Timer synchronization (TIM12)

The TIM timers are linked together internally for timer synchronization or chaining. Refer to

Section 13.3.15: Timer synchronization

The clock of the slave timer must be enabled prior to receive events from the master timer,

and must not be changed on-the-fly while triggers are received from the master timer.

When the microcontroller enters debug mode (Cortex

either continues to work normally or stops, depending on DBG_TIMx_STOP configuration

bit in DBG module. For more details, refer to

watchdog and I

RM0041 Rev 6

General-purpose timers (TIM12/13/14)

for details.

-M3 core halted), the TIMx counter

Section 25.15.2: Debug support for timers,

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