Debug Mode; Figure 133. Triggering Tim3 And Tim2 With Tim3 Ti1 Input - ST STM32F100 Series Reference Manual

General-purpose timers (TIM2 to TIM5)
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of TIM3 when its TI1 input rises, and the enable of TIM2
with the enable of TIM3. Refer to
aligned, TIM3 must be configured in Master/Slave mode (slave with respect to TI1, master
with respect to TIM2):
•
Configure TIM3 master mode to send its Enable as trigger output (MMS=001 in the
TIM3_CR2 register).
•
Configure TIM1 slave mode to get the input trigger from TI1 (TS=100 in the
TIM3_SMCR register).
•
Configure TIM3 in trigger mode (SMS=110 in the TIM3_SMCR register).
•
Configure the TIM3 in Master/Slave mode by writing MSM=1 (TIM3_SMCR register).
•
Configure TIM2 to get the input trigger from TIM3 (TS=000 in the TIM2_SMCR
register).
•
Configure TIM2 in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (TIM3), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but the user can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). The master/slave mode inserts a delay
between CNT_EN and CK_PSC on TIM3.
TIM3-CEN=CNT_EN
TIM2-CEN=CNT_EN
13.3.16

Debug mode

When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBGMCU module. For more details, refer to
timers, watchdog and I
320/709

Figure 133. Triggering TIM3 and TIM2 with TIM3 TI1 input

CK_INT
TIM3-TI1
TIM3-CK_PSC
TIM3-CNT
TIM3-TIF
TIM2-CK_PSC
TIM2-CNT
TIM2-TIF
2
C.
Figure 128 for connections. To ensure the counters are
00 01
00 01 02 03 04 05 06 07 08 09
®
Section 25.15.2: Debug support for
RM0041 Rev 6
02 03 04 05 06 07 08 09
-M3 core - halted), the TIMx counter
RM0041
MS33123V1