Figure 129. Gating Tim2 With Oc1Ref Of Tim3 - ST STM32F100 Series Reference Manual

RM0041
For example, the user can configure TIM3 to act as a prescaler for TIM2. Refer to
Figure 128. To do this:
•
Configure TIM3 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If MMS=010 is written in the TIM3_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
•
To connect the TRGO1 output of TIM3 to TIM2, TIM2 must be configured in slave mode
using ITR2 as internal trigger. Select this through the TS bits in the TIM2_SMCR
register (writing TS=010).
•
Then put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIM2_SMCR register). This causes TIM2 to be clocked by the rising edge of the
periodic TIM3 trigger signal (which correspond to the TIM3 counter overflow).
• Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note: If OCx is selected on TIM3 as the trigger output (MMS=1xx), its rising edge is used to clock
the counter of TIM2.
Using one timer to enable another timer
In this example, we control the enable of TIM2 with the output compare 1 of Timer 1. Refer
to Figure 128
of TIM3 is high. Both counter clock frequencies are divided by 3 by the prescaler compared
to CK_INT (f
•
Configure TIM3 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM3_CR2 register).
• Configure the TIM3 OC1REF waveform (TIM3_CCMR1 register).
•
Configure TIM2 to get the input trigger from TIM3 (TS=010 in the TIM2_SMCR
register).
•
Configure TIM2 in gated mode (SMS=101 in TIM2_SMCR register).
•
Enable TIM2 by writing '1 in the CEN bit (TIM2_CR1 register).
•
Start TIM3 by writing '1 in the CEN bit (TIM3_CR1 register).
Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the TIM2
counter enable signal.
TIM3-OC1REF
In the example in
started. So they start counting from their current value. It is possible to start from a given
for connections. TIM2 counts on the divided internal clock only when OC1REF
= f /3).
CK_CNT CK_INT

Figure 129. Gating TIM2 with OC1REF of TIM3

CK_INT
TIM3-CNT
FC
TIM2-CNT
3045
TIM2-TIF
Write TIF = 0
Figure 129, the TIM2 counter and prescaler are not initialized before being
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General-purpose timers (TIM2 to TIM5)
FD FE FF
3046 3047
00 01
3048
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