Packet Error Checking; I 2 C Interrupts; Table 122. I2C Interrupt Requests - ST STM32F100 Series Reference Manual

Inter-integrated circuit (I2C) interface
22.3.8

Packet error checking

A PEC calculator has been implemented to improve the reliability of communication. The
PEC is calculated by using the C(x) = x
•
PEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a
CRC-8 calculated on all message bytes including addresses and R/W bits.
–
–
•
A PECERR error flag/interrupt is also available in the I2C_SR1 register.
•
If DMA and PEC calculation are both enabled:-
–
–
•
To allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register
(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA
request for a master receiver, a NACK is automatically sent after the last received byte.
•
PEC calculation is corrupted by an arbitration loss.
2
22.4 I C interrupts
The table below gives the list of I
Start bit sent (Master)
Address sent (Master) or Address matched (Slave)
10-bit header sent (Master)
Stop received (Slave)
Data byte transfer finished
Receive buffer not empty
Transmit buffer empty
584/709
In transmission: set the PEC transfer bit in the I2C_CR1 register after the TxE
event corresponding to the last byte. The PEC is transferred after the last
transmitted byte.
In reception: set the PEC bit in the I2C_CR1 register after the RxNE event
corresponding to the last byte so that the receiver sends a NACK if the next
received byte is not equal to the internally calculated PEC. In case of Master-
Receiver, a NACK must follow the PEC whatever the check result.The PEC must
be set before the ACK pulse of the current byte reception.
In transmission: when the I
controller, it automatically sends a PEC after the last byte.
In reception: when the I
controller, it automatically considers the next byte as a PEC and checks it. A DMA
request is generated after PEC reception.
Table 122. I
Interrupt event
8 2
+ x + x + 1 CRC-8 polynomial serially on each bit.
2
C interface receives an EOT signal from the DMA
2
C interface receives an EOT_1 signal from the DMA
2
C interrupt requests.
2
C Interrupt requests
Event flag
ADDR
ADD10
STOPF
RxNE
RM0041 Rev 6
Enable control bit
SB
ITEVFEN
BTF
ITEVFEN and ITBUFEN
TxE
RM0041