ST STM32F100 Series Reference Manual page 325

RM0041
Bit 7 MSM: Master/Slave mode
Bits 6:4 TS: Trigger selection
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
Bit 3 OCCS: OCREF clear selection
Bits 2:0 SMS: Slave mode selection
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0).
001: Internal Trigger 1 (ITR1).
010: Internal Trigger 2 (ITR2).
011: Internal Trigger 3 (ITR3).
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 71: TIMx internal trigger connection on page 326
meaning for each Timer.
avoid wrong edge detections at the transition.
This bit is used to select the OCREF clear source
0: OCREF_CLR_INT is connected to the OCREF_CLR input
1: OCREF_CLR_INT is connected to ETRF
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control register
description.
000: Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
The clock of the slave timer must be enabled prior to receiving events from the master
timer, and must not be changed on-the-fly while triggers are received from the master
timer.
General-purpose timers (TIM2 to TIM5)
RM0041 Rev 6
for more details on ITRx
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