Memory Map; Table 1. Low And Medium-Density Device Register Boundary Addresses - ST STM32F100 Series Reference Manual

RM0041
2.3

Memory map

See the datasheet corresponding to the used device for a comprehensive diagram of the
memory map.
in all STM32F100xx devices.

Table 1. Low and medium-density device register boundary addresses

Boundary address
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0000 - 0x4002 03FF
0x4001 4C00 - 0x4001 FFFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0x4001 1C00 - 0x4001 23FF
0x4001 1800 - 0x4001 1BFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0C00 - 0x4001 0FFF
0x4001 0800 - 0x4001 0BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
Table 1 and Table 2 give the boundary addresses of the peripherals available
Peripheral
CRC
Reserved
Flash memory interface
Reserved
Reset and clock control RCC
Reserved
DMA1
Reserved
TIM17 timer
TIM16 timer
TIM15 timer
Reserved
USART1
Reserved
SPI1
TIM1 timer
Reserved
ADC1
Reserved
GPIO Port E
GPIO Port D
GPIO Port C
GPIO Port B
GPIO Port A
EXTI
AFIO
RM0041 Rev 6
Memory and bus architecture
Bus Register map
Section 3.4.4 on page 49
AHB
Section 6.3.12 on page 101
Section 9.4.7 on page 159
Section 15.6.16 on page 454
Section 15.6.16 on page 454
Section 15.5.18 on page 434
Section 23.6.8 on page 646
Section 21.4.8 on page 565
Section 12.4.21 on page 282
APB2
Section 10.11.15 on page 188
Section 7.5 on page 130
Section 7.5 on page 130
Section 7.5 on page 130
Section 7.5 on page 130
Section 7.5 on page 130
Section 8.3.7 on page 143
Section 7.5 on page 130
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