ST STM32F100 Series Reference Manual page 706

Revision history
Date
10-Jun-2016
12-Dec-2022
706/709
Table 161. Document revision history (continued)
Revision
Updated:
– Mode 1 - SRAM/PSRAM
flash memory, PSRAM,
Flash chip-select timing registers 1..4
Flash write timing registers 1..4
chip-select control registers 1..4
flash/PSRAM controller asynchronous transactions
NOR/PSRAM control
Replaced M/SL with MSL throughout
(I2C) interface, and updated
5
(I2C_CR1), Section 22.6.2: I
continued
Section 22.6.9: I
Replaced nCTS with CTS, nRTS with RTS and SCLK with CK throughout
Section 27: Universal synchronous asynchronous receiver transmitter
(USART).
Updated:
– Section 27.3.8: LIN (local interconnection network)
proper oversampling
USART_BRR register values when OVER8=0
USARTDIV from USART_BRR register values when OVER8=1
Section 27.6.6: Control register 3
Updated Introduction,
Section 5.2: BKP main
Section 12.3.21: Debug
mode register 1
register 1 (TIMx_CCR1),
4 (TIMx_CCR4),
(TIMx_DMAR),
(TIMx_CCMR1), sections
capture/compare mode register 1
14.4.13, Section 14.5.9: TIM13/14 auto-reload register
Section 14.5.10: TIM13/14 capture/compare register 1
6
Section 15.5.5: TIM15 status register
TIM16&TIM17 capture/compare register 1
Section 19.4: How to program the watchdog
Added Section 1.4: General information
notice.
Updated Table 14: BKP register map and reset values
register map and reset
Updated Figure 6: PVD
block diagram,
and Figure 259: Parity error detection using the 1.5 stop
Minor text edits across the whole document.
RM0041 Rev 6
Changes
(CRAM), Asynchronous static memories (NOR
SRAM), , Mode 2/B - NOR
(FSMC_BWTR1..4),
(FSMC_BCR1..4),
registers.
Section 22: Inter-integrated circuit
Section 22.6.1: I
2
C Control register 2 (I2C_CR2)
2
C TRISE register (I2C_TRISE).
method, How to derive USARTDIV from
(USART_CR3).
Section 4.4.1: Power control register
features, Section 5.4: BKP
mode, Section 12.4.7: TIM1 capture/compare
(TIMx_CCMR1), Section 12.4.14: TIM1 capture/compare
Section 12.4.17: TIM1 capture/compare register
Section 12.4.20: TIM1 DMA address for full transfer
Section 13.4.7: TIMx capture/compare mode register 1
13.4.13 to 13.4.16,
(TIMx_CCMR1), sections
(TIM15_SR),
values.
thresholds, Figure 40: Advanced-control timer
Figure 134: General-purpose timer block diagram
flash, SRAM/NOR-
(FSMC_BTR1..4), SRAM/NOR-
SRAM/NOR-flash
Section 20.5.4: NOR
and Section 20.5.6:
2
C Control register 1
and
mode, Selecting the
and How to derive
(PWR_CR),
registers,
Section 14.4.7: TIM
14.4.11
(TIMx_ARR),
(TIMx_CCR1),
Section 15.6.12:
(TIMx_CCR1), and
timeout.
and Section 27: Important security
and Table 69: TIM1
bits.
RM0041
and
to
(TIM12),