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RM0041
9.4.2
DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
Reserved
15
14
13
12
CTEIF
CHTIF
CTCIF
CGIF4
4
4
4
w
w
w
Bits 31:28
Reserved, must be kept at reset value.
Bits 27, 23, 19, 15,
CTEIFx: Channel x transfer error clear (x = 1 ..7)
11, 7, 3
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 26, 22, 18, 14,
CHTIFx: Channel x half transfer clear (x = 1 ..7)
10, 6, 2
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 25, 21, 17, 13,
CTCIFx: Channel x transfer complete clear (x = 1 ..7)
9, 5, 1
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 24, 20, 16, 12,
CGIFx: Channel x global interrupt clear (x = 1 ..7)
8, 4, 0
This bit is set and cleared by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
27
26
25
CTEIF
CHTIF
CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5
7
7
w
w
w
11
10
9
CTEIF
CHTIF
CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1
3
3
w
w
w
w
Direct memory access controller (DMA)
24
23
22
w
w
w
8
7
6
w
w
w
RM0041 Rev 6
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
17
16
w
w
1
0
w
w
155/709
161
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