Figure 77. Output Behavior In Response To A Break - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus

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Advanced-control timer (TIM1)

(OCxN not implemented, CCxP=0, OISx=1)

(OCxN not implemented, CCxP=0, OISx=0)

(OCxN not implemented, CCxP=1, OISx=1)

(OCxN not implemented, CCxP=1, OISx=0)

(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)

(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)

(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)

(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)

(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)

shows an example of behavior of the outputs in response to a break.

Figure 77. Output behavior in response to a break.

RM0041 Rev 6

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