Figure 44. Counter Timing Diagram, Internal Clock Divided By 2; Figure 45. Counter Timing Diagram, Internal Clock Divided By 4; Figure 46. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F100 Series Reference Manual

Advanced-control timer (TIM1)
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Figure 44. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 45. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 46. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
0034 0035 0036
0035 0036
1F 20
RM0041 Rev 6
0000 0001 0002 0003
0000 0001
00
RM0041
MS31079V3
MS31080V3
MS31081V3